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summit microelectronics, inc. ? 300 orchard city drive, suite 131 campbell, ca 95008 telephone 408-378- 6461 fax 408-378-6586 www.summitmicro.com 1 ? summit microelectronics, inc. 2000 2011 2.1 8/2/00 characteristics subject to change without notice summit microelectronics, inc. features ? precision supply voltage monitor ? dual reset outputs for complex microcontroller systems ? integrated memory write lockout guaranteed reset (reset#) assertion to v cc =1v power-fail accuracy guaranteed no external components 3 and 5 volt system versions low power cmos ? active current less than 3ma ? standby current less than 25a memory internally organized 512 x 8 ? two wire serial interface (i 2 c?) ? bidirectional data transfer protocol ? standard 100khz and fast 400khz precision reset controller and 4k i 2 c memory with both reset and reset reset reset reset reset outputs s24042/s24043 high reliability ? endurance: 100,000 erase/write cycles ? data retention: 100 years 8-pin soic packages overview the s24042 and s24043 are power supervisory devices with 4,096 bits of serial e 2 prom. they are fabricated using summit?s advanced cmos e 2 prom technology and are suitable for both 3 and 5 volt systems. the memory is internally organized as 512 x 8. it features the i 2 c serial interface and software protocol allowing operation on a simple two-wire bus. the s24042 provides a precision v cc sense circuit and two open drain outputs: one (reset) drives high and the other (reset#) drives low whenever v cc falls below v trip . the s24043 is identical to the s24042 with the exception being reset is not bonded out on pin 7. block diagram 3 and 5 volt systems + ? gnd v cc reset# v trip reset pulse generator 5khz oscillator reset control mode decode address decoder write control data i/o e 2 prom memory array reset 1.26v scl 6 sda 5 2 7 22 2011 t-bd 1.0 4
2 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. reset #- reset# is an active low open drain output. it is driven low whenever v cc is below v trip . it is also an input and can be used to debounce a switch input or perform signal conditioning. the pin has an internal pull- up and should be left unconnected if the signal is not used in the system. however, when the pin is tied to a system reset# line an external pull-up resistor should be employed. reset - reset is an active high open drain output. it is driven high whenever v cc is below v trip . reset is also an input and can be used to debounce a switch input or perform signal conditioning. the reset pin does have an internal pull-down and should be left unconnected if the signal is not used in the system. however, when the pin is tied to a system reset line an external pull-down resistor should be employed. endurance and data retention the s24042/43 is designed for applications requiring 100,000 erase/write cycles and unlimited read cycles. it provides 100 years of secure data retention, with or without power applied, after the execution of 100,000 erase/write cycles. applications reset controller description the s24042/43 provides a precision reset controller that ensures correct system operation during brown-out and power-up/-down conditions. it is configured with two open drain reset outputs; pin 7 is an active high output and pin 2 is an active low output. during power-up, the reset outputs remain active until v cc reaches the v trip threshold and will continue driving the outputs for approximately 200ms after reaching v trip . the reset outputs will be valid so long as v cc is > 1.0v. during power-down, the reset outputs will begin driving active when v cc falls below v trip . the reset pins are i/os; therefore, the s24042/43 can act as a signal conditioning circuit for an externally applied reset. the inputs are edge triggered; that is, the reset input will initiate a reset timeout after detecting a low to high transition and the reset# input will initiate a reset timeout after detecting a high to low transition. refer to the applications information section for more details on device operation as a reset conditioning circuit. pin descriptions serial clock (scl) - the scl input is used to clock data into and out of the device. in the write mode, data must remain stable while scl is high. in the read mode, data is clocked out on the falling edge of scl. serial data (sda) - the sda pin is a bidirectional pin used to transfer data into and out of the device. data may change only when scl is low, except start and stop conditions. it is an open-drain output and may be wire- ored with any number of open-drain or open-collector outputs. no connects (nc) the no connect pins may be left floating or tied to ground. they cannot be tied high. pin names sda serial data i/o scl serial clock input reset & reset# reset output v ss ground v cc supply voltage nc no connect pin configurations 8 7 6 5 1 2 3 4 nc reset# nc v ss v cc nc scl sda nc reset# nc v ss v cc reset scl sda 8 7 6 5 1 2 3 4 s24043 s24042 2011 pcon 2.0
s24042/s24043 3 2011 2.1 8/2/00 summit microelectronics, inc. figure 1. typical system configuration for dual reset figure 2. start and stop conditions scl sda in start condition stop condition 2011 ill5 1.0 reset scl sda scl vss vcc = 3.0 0r 5.0 8051 type mcu s24042 i c peripheral 2 2 1 3 4 7 8 6 5 2011 t fig01 2.0 vcc reset sda scl sda reset# reset#
4 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. figure 3. acknowledge response from receiver characteristics of the i 2 c bus general description the i 2 c bus was designed for two-way, two-line serial communication between different integrated circuits. the two lines are: a serial data line (sda), and a serial clock line (scl). the sda line must be connected to a positive supply by a pull-up resistor, located somewhere on the bus (see figure 1). data transfer between devices may be initiated with a start condition only when scl and sda are high (bus is not busy). input data protocol one data bit is transferred during each clock pulse. the data on the sda line must remain stable during clock high time, because changes on the data line while scl is high will be interpreted as start or stop condition, refer to figure 10. start and stop conditions when both the data and clock lines are high, the bus is said to be not busy. a high-to-low transition on the data line, while the clock is high, is defined as the ? start ? condition. a low-to-high transition on the data line, while the clock is high, is defined as the ? stop ? condi- tion (see figure 2). device operation the s24042/43 is a 4,096-bit serial e 2 prom. the device supports the i 2 c bidirectional data transmission protocol. the protocol defines any device that sends data onto the bus as a ? transmitter ? and any device which receives data as a ? receiver. ? the device controlling data transmission is called the ? master ? and the controlled device is called the ? slave. ? in all cases, the s24042/43 will be a ? slave ? device, since it never initiates any data transfers. figure 4. slave address byte acknowledge (ack) acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either the master or the slave, will release the bus after transmit- ting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it re- ceived the eight bits of data (see figure 3). the s24042/43 will respond with an acknowledge after recognition of a start condition and its slave address byte. if both the device and a write operation are selected, the s24042/43 will respond with an acknowledge after the receipt of each subsequent 8-bit word. in the read mode, the s24042/43 transmits eight bits of data, then releases the sda line, and monitors the line for an acknowledge signal. if an acknowledge is detected, and no stop condition is generated by the master, the s24042/43 will continue to transmit data. if an acknowledge is not detected, the s24042/43 will termi- nate further data transmissions and awaits a stop condi- tion before returning to the standby power mode. device addressing following a start condition the master must output the address of the slave it is accessing. the most significant four bits of the slave address are the device type identifier (see figure 4). for the s24042/43 this is fixed as 1010[b]. the next two bits are don ? t care. the next bit is the high order address bit a8. scl from master data output from transmitter data output from receiver start condition acknowledge t aa t aa 1 8 9 2011 ill6 1.0 1 0 1 0 x x r/w device identifier don ? t care 2011 ill7 1.1 a 8
s24042/s24043 5 2011 2.1 8/2/00 summit microelectronics, inc. figure 5. page/byte write mode write operations the s24042/43 allows two types of write operations: byte write and page write. the byte write operation writes a single byte during the nonvolatile write period (t wr ). the page write operation allows up to 16 bytes in the same page to be written during t wr . byte write upon receipt of the slave address and word address, the s24042/43 responds with an acknowledge. after receiv- ing the next byte of data, it again responds with an acknowledge. the master then terminates the transfer by generating a stop condition, at which time the s24042/43 begins the internal write cycle. while the internal write cycle is in progress, the s24042/ 43 inputs are disabled, and the device will not respond to any requests from the master. refer to figure 5 for the address, acknowledge and data transfer sequence. page write the s24042/43 is capable of a 16-byte page write opera- tion. it is initiated in the same manner as the byte-write operation, but instead of terminating the write cycle after the first data word, the master can transmit up to 15 more bytes of data. after the receipt of each byte, the s24042/ 43 will respond with an acknowledge. the s24042/43 automatically increments the address for subsequent data words. after the receipt of each word, the low order address bits are internally incremented by one. the high order five bits of the address byte remain constant. should the master transmit more than 16 bytes, prior to generating the stop condition, the address counter will ? roll over, ? and the previously written data will be overwritten. as with the byte-write operation, all inputs are disabled during the internal write cycle. refer to figure 5 for the address, acknowledge and data transfer sequence. read/write bit the last bit of the data stream defines the operation to be performed. when set to ? 1, ? a read operation is selected; when set to ? 0, ? a write operation is selected. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 8 a 8 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 5 d 6 d 4 d 0 d 3 d 2 d 1 s t a r t word address data byte n data byte n+15 s t o p a c k acknowledges transmitted from 24042/43 to master receiver slave address device type address read/write 0= write sda bus activity a c k a c k master sends read request to slave master writes word address to slave 1 0 1 0 0 data byte n+1 a c k master writes data to slave master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver shading denotes 24042/43 sda output active master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver slave transmitter to master receiver master writes data to slave master writes data to slave acknowledges transmitted from 24042/43 to master receiver if single byte-write only, stop bit issued here. xx r w a c k 2011 ill8 1.0
6 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. figure 7. current address byte read mode figure 6. acknowledge polling acknowledge polling when the s24042/43 is performing an internal write operation, it will ignore any new start conditions. since the device will only return an acknowledge after it accepts the start, the part can be continuously queried until an acknowledge is issued, indicating that the internal write cycle is complete. to poll the device, give it a start condition, followed by a slave address for a write operation (see figure 6). read operations read operations are initiated with the r/w bit of the identification field set to ? 1. ? there are four different read options: 1. current address byte read 2. random address byte read 3. current address sequential read 4. random address sequential read current address byte read the s24042/43 contains an internal address counter which maintains the address of the last word accessed, incremented by one. if the last address accessed (either a read or write) was to address location n, the next read operation would access data from address location n+1 and increment the current address pointer. when the s24042/43 receives the slave address field with the r/w bit set to ? 1, ? it issues an acknowledge and transmits the 8-bit word stored at address location n+1. the current address byte read operation only accesses a single byte of data. the master does not acknowledge the transfer, but does generate a stop condition. at this point, the s24042/43 discontinues data transmission. see fig- ure 7 for the address acknowledge and data transfer sequence. issue start internal write cycle in progress; begin ack polling issue slave address and r/w = 0 ack returned? next operation a write? issue byte address proceed with write issue stop await next command issue stop no no yes (internal write cycle is completed) yes 2011 ill9 1.0 s t a r t s t o p slave address device type address read/write 1= read sda bus activity d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 master sends read request to slave slave sends data to master master transmitter to slave receiver slave transmitter to master receiver 1 1 1 00 1 lack of ack (low) from master determines last data byte to be read 1 shading denotes 24042/43 sda output active x x r w a c k x data byte 2011 ill 10 1.0
s24042/s24043 7 2011 2.1 8/2/00 summit microelectronics, inc. figure 8. random address byte read mode random address byte read random address read operations allow the master to access any memory location in a random fashion. this operation involves a two-step process. first, the master issues a write command which includes the start condi- tion and the slave address field (with the r/w bit set to write) followed by the address of the word it is to read. this procedure sets the internal address counter of the s24042/43 to the desired address. after the word address acknowledge is received by the master, the master immediately reissues a start condition followed by another slave address field with the r/w bit set to read. the s24042/43 will respond with an ac- knowledge and then transmit the 8-data bits stored at the addressed location. at this point, the master does not acknowledge the transmission but does generate the stop condition. the s24042/43 discontinues data transmis- sion and reverts to its standby power mode. see figure 8 for the address, acknowledge and data transfer se- quence. d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 8 a 8 a 6 a 5 a 4 a 3 a 2 a 1 a 0 s t a r t word address s t o p a c k slave address slave address device type address read/write 0= write device type address sda bus activity s t a r t read/write 1= read a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master 1010 1010 1 0 xx r w x r w xx lack of ack (low) from master determines last data byte to be read 1 slave transmitter to master receiver slave transmitter to master receiver shading denotes 24042/43 sda output active slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver data byte 2011 ill11 1.0
8 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted as with the other byte read modes (current address byte read or random address byte read); however, the master now responds with an acknowledge, indicating that it requires additional data from the s24042/43. the s24042/43 continues to output data for each acknowledge received. the master terminates the sequential read operation by not responding with an acknowledge, and issues a stop conditions. during a sequential read operation, the internal address counter is automatically incremented with each acknowl- edge signal. for read operations, all address bits are incremented, allowing the entire array to be read using a single read command. after a count of the last memory address, the address counter will ? roll-over ? and the memory will continue to output data. see figure 9 for the address, acknowledge and data transfer sequence. figure 9. sequential read operation (starting with a random address read) d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 7 a 8 a 8 a 6 a 5 a 4 a 3 a 2 a 1 a 0 shading denotes 24042/43 sda output active s t a r t word address s t o p a c k acknowledges from 24042/43 slave address slave address device type address read/write 0= write device type address sda bus activity s t a r t read/write 1= read x r w x acknowledge from master receiver a c k a c k a c k master sends read request to slave master writes word address to slave master requests data from slave slave sends data to master slave transmitter to master receiver slave transmitter to master receiver master transmitter to slave receiver 1010 1010 1 0 slave sends data to master xx r w lack of ack (low) determines last data byte to be read 1 lack of acknowledge from master receiver slave transmitter to master receiver master transmitter to slave receiver master transmitter to slave receiver master transmitter to slave receiver slave transmitter to master receiver slave transmitter to master receiver last data byte first data byte 2011 t fig09 2.0 a 8
s24042/s24043 9 2011 2.1 8/2/00 summit microelectronics, inc. absolute maximum ratings temperature under bias ......................................................................................................... ...................... -40 c to +85 c storage temperature ............................................................................................................ ......................... -65 c to +125 c soldering temperature (less than 10 seconds) ................................................................................... ................................ 300 c supply voltage ................................................................................................................. ............................................ 0 to 6.5v voltage on any pin ............................................................................................................. .......................... -0.3v to v cc +0.3v esd voltage (jedec method) ..................................................................................................... ..................................... 2,000v note: these are stress ratings only. appropriate conditions for operating these devices are given elsewhere in this specificati on. stresses beyond those listed here may permanently damage the part. prolonged exposure to maximum ratings may affect device reliability. 2.7v to 4.5v 4.5v to 5.5v symbol parameter conditions min max min max units f scl scl clock frequency 0 100 400 khz t low clock low period 4.7 1.3 s t high clock high period 4.0 0.6 s t buf bus free time before new transmission 4.7 1.3 s t su:sta start condition setup time 4.7 0.6 s t hd:sta start condition hold time 4.0 0.6 s t su:sto stop condition setup time 4.7 0.6 s t aa clock to output scl low to sda data out valid 0.3 3.5 0.2 0.9 s t dh data out hold time scl low to sda data out change 0.3 0.2 s t r scl and sda rise time 1000 300 ns t f scl and sda fall time 300 300 ns t su:dat data in setup time 250 100 ns t hd:dat data in hold time 0 0 ns t i noise spike width noise suppression time constant 100 100 ns @ scl, sda inputs t wr write cycle time 10 10 ms ac electrical characteristics (over recommended operating conditions unless otherwise specified) 2011 pgm t2 1.0 2011 pgm t1 1.0 dc electrical characteristics (over recommended operating conditions unless otherwise specified) symbol parameter conditions min max units scl = cmos levels @ 100khz v cc =5.5v 3 ma i cc supply current (cmos) sda = open all other inputs = gnd or v cc v cc =3.3v 2 ma i sb standby current (cmos) scl = sda = v cc v cc =5.5v 50 a all other inputs = gnd i li input leakage v in = 0 to v cc 10 a i lo output leakage v out = 0 to v cc 10 a v il input low voltage scl, sda, reset 0.3xv cc v v ih input high voltage scl, sda 0.7xv cc v v ol output low voltage i ol = 3ma sda 0.4 v v cc =3.3v 25 a characteristic min max v cc 2.7v 5.5v operating temperature range ? 40 c85 c recommended operating conditions 2011 pgm t6 1.0
10 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. figure 10. bus timing capacitance t a = 25 c, f = 100khz symbol parameter max units c in input capacitance 5 pf c out output capacitance 8 pf 2011 pgm t3 1.0 scl sda in sda out t aa t r t h igh t low t su:sto t buf t su:dat t hd:dat t hd:sda t su:sda t dh 2011 ill 13 1.0 t f
s24042/s24043 11 2011 2.1 8/2/00 summit microelectronics, inc. figure 11. reset output timing s24042/43-2.7 s24042/43 ? a s24042/43 ? b symbol parameter min max min max min max unit v trip reset trip point 2.55 2.7 4.25 4.5 4.5 4.75 v t purst power-up reset timeout 130 270 130 270 130 270 ms t rpd v trip to reset output delay 5 5 5 s v rvalid reset# output valid 1 1 1 v t glitch glitch reject pulse width 30 30 30 ns v olrs reset# output low voltage i ol = 1ma 0.4 0.4 0.4 v v ohrs reset output high voltage i oh = 800 a v cc -.75 v cc -.75 v cc -.75 v reset circuit ac and dc electrical characteristics t a = -40 c to +85 c 2011 pgm t6 1.1 v cc v rvalid v trip t purst reset# reset 2011 t fig11 2.0 t glitch t rpd t purst t rpd s24042 only
12 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. frequently the reset controller will be deployed on a pc board that provides a peripheral function to a system. examples might be modem or network cards in a pc or a pcmcia card in a laptop. in instances like this the peripheral card may have a requirement for a clean reset function to insure proper operation. the system may or may not provide a reset pulse of sufficient duration to clear the peripheral or to protect data stored in a nonvolatile memory. the i/o capability of the reset pins can provide a solution. the system ? s reset signal to the peripheral can be fed into the s24042/43 and it in turn can clean up the signal and provide a known entity to the peripheral ? s circuits. the figure below shows the basic timing characteristics under the assumption the reset input is shorter in duration than t purst . the same reset output affect can be attained by using the active high reset input. when planning your resistor pull-up and pull-down values, use the following chart to help determine min. resistances. condition min typ max units v cc = 1.0v, i ol =100a 0.3 v v cc = 1.2v, i ol =100a 0.3 v v cc = 3.0v, i ol =500a 0.3 v v cc = 3.6v, i ol =500a 0.3 v v cc = 4.5v, i ol =750a 0.3 v v cc = 1.0v, i ol =100a 0.4 v v cc = 1.2v, i ol =150a 0.4 v v cc = 3.0v, i ol =750a 0.4 v v cc = 3.6v, i ol =1ma 0.4 v v cc = 4.5v, i ol =1ma 0.4 v v cc = 1.0v, i oh =400a v cc -0.75 v v cc = 1.2v, i oh =800a v cc -0.75 v v cc = 3.0v, i oh =800a v cc -0.5 v v cc = 3.6v, i oh =800a v cc -0.5 v v cc = 4.5v, i oh =800a v cc -0.5 v worst case reset sink/source capabilities at various v cc levels parameter symbol reset# output v ol voltage reset# output v ol voltage reset output v oh voltage 2011 pgm t5 1.0 reset# input reset# output reset output 2011 t fig12 2.0 t purst
s24042/s24043 1 3 2011 2.1 8/2/00 summit microelectronics, inc. .228 (5.80) .244 (6.20) .016 (.40) .035 (.90) .020 (.50) .010 (.25) x45 .0192 (.49) .0138 (.35) .061 (1.75) .053 (1.35) .0098 (.25) .004 (.127) .05 (1.27) typ. .275 (6.99) typ. .030 (.762) typ. 8 places .050 (1.27) typ. .050 (1.270) typ. 8 places .157 (4.00) .150 (3.80) .196 (5.00) 1 .189 (4.80) footprint 8pn jedec soic ill.2 8 pin soic (type s) package jedec (150 mil body width)
14 s24042/s24043 2011 2.1 8/2/00 summit microelectronics, inc. ordering information notice summit microelectronics, inc. reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. summit microelectronics, inc. assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a user ? s specific application. while the information in this publication has been carefully checked, summit microelectronics, inc. shall not be liable for any damages arising as a result of any error or omission. summit microelectronics, inc. does not recommend the use of any of its products in life support or aviation applications where the failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their safety or effectiveness. products are not authorized for use in such applications unless summit microelectronics, inc. receives written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; and (c) potential liability of summit microelectronics, inc. is adequately protected under the circumstances. ? copyright 2000 summit microelectronics, inc. i 2 c is a trademark of philips corporation. s24022 s a t base part number tape & reel option operating voltage range package s = 8 lead 150mil soic blank = tube t = tape & reel a = 4.5v to 5.5v v trip min. @ 4.25v b = 4.5v to 5.5v v trip min. @ 4.50v 2.7 = 2.7v to 5.5v v trip min. @ 2.55v s24022 = reset active high & low s24023 = reset active low 2011 tree 2.0

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